1. Technical Field
The present invention relates to a programmable logic device, and more particularly to a multiplexer for a programmable logic device.
2. Description of the Related Art
Programmable logic devices (PLDs) typically make use of one or more interconnect arrays that are programmed via an array of memory cells (e.g. EPROM, EEPROM, flash EPROM, or flash EEPROM cells) to make the various interconnections within the PLD that are specific to a desired design. Because advances in the art allow regular increases in the complexity of PLDs, the size of the programmable interconnect array must also be increased to achieve the desired PLD complexity.
Unfortunately, a significant amount of the power and die size is consumed in the programmable elements of the programmable interconnect array. Additionally, the programmable interconnect array introduces a significant speed limitation due to capacitive loading by the programmable elements used therein. Thus, increasing the size of the programmable interconnect array leads to higher power consumption and lower PLD speed. Thus, as larger PLDs are designed, the programmable elements themselves become an increasingly critical, limiting factor.
FIG. 1 illustrates a portion 100 of a typical PLD that includes a universal interconnect matrix (UIM) 104 and an interconnect multiplexer 101. In FIG. 1, I/O pads 105 are coupled either to UIM 104 or multiplexer 101 (via TTL buffers 112). Signals received by multiplexer 101 are provided to AND array 102. AND array 102 generates the product terms that drive a plurality of macrocells 103. Macrocells 103 are coupled to I/O pads 106, multiplexer 101 (via feedback lines 107), or UIM 104 (via feedback lines 108). UIM 104 provides a programmable signal path between macrocells 103 and I/O pads 105 (via feedback lines 110) as well as multiplexer 101 (via feedback lines 109). The PLD also includes various timing and control pads (note shown) which provide clock and enable signals to multiplexer 101 and macrocells 103.
One problem with this PLD is that multiplexer 101 requires a discrete control signal for each multiplexer connection. While this arrangement is acceptable for PLD designs that only require a small number of multiplexers, PLD designs that require a larger number of multiplexers also require a larger number of control signals. For example, multiplexers are typically arranged in arrays that have 450 multiplexer connections (126 input lines.times.3 connections per input line (includes both input pad and feedback connections)+36 ground connections+36 UIM connections). A typical PLD may have up to six such multiplexers, therefore requiring 2700 multiplexer connections, which in turn necessitate 2700 control signals. The routing of these control signals through a PLD is undesirably complex.
Conventional multiplexers allow only two entry points for any multiplexer input line to any multiplexer output line. In other words, each input line in a prior art multiplexer is connectable to 2 output lines. If a specific user design requires that several input signals must be routed into a function block (which includes multiplexer 101, AND array 102 and macrocells 103), it becomes exceedingly difficult to route signals through the multiplexer successfully. If routing through the multiplexer is impossible, then various multiplexer input signals, typically under control of the programming software that is used to configure the PLD, must be switched to different lines. In such case, the input lines are accessed via different multiplexer ports. Unfortunately, this approach is undesirable because:
a. If an input signal is an external signal that is received via a specific PLD pin, it may not be possible to place the signal on the desired pin; PA1 b. If an input signal is received from a macrocell within the PLD, the signal must be placed in a different macrocell, thereby exacerbating the placement problem; and PA1 c. Moving an input signal to a different input line of the multiplexer implies that the signal is moved globally, i.e. for all multiplexers associated with all other function blocks. For large PLDs, there are many function blocks, thereby increasing the probability that a particular routing for one multiplexer adversely affects the routing of the other multiplexers to which the signal is propagated.
Therefore, a need arises for a multiplexer that provides efficient and flexible control and routing options to allow reliable implementation of complex user designs without adding unnecessary complexity to the PLD, or substantially increasing the PLD size or power requirements.